This invention relates to a semiconductor device having a semiconductor integrated circuit laid out on a semiconductor substrate based on a basic cell library having basic cells of novel structure and a method for manufacturing the same.
A semiconductor device is manufactured basically via a design process (function design, logic design, layout design and the like) and a manufacturing and test process (chip manufacturing process, test evaluation process and the like). The design process is effected in an order of function design.fwdarw.logic design.fwdarw.layout design.
At present, the process technology of the semiconductor device enters upon the deep submicron generation. Under this situation, the width of wirings used in the semiconductor device is reduced to 0.3 .mu.m or less. However, for example, a reduction in the wiring width of the polysilicon wiring (which is hereinafter referred to as the poly-width) or the like causes a problem that a minute variation in the poly-width caused by the optical proximity effect cannot be neglected.
The optical proximity effect (OPE) is a phenomenon that the finish value of the poly-width W of the polysilicon wiring will vary according to a space d between the polysilicon wiring and an adjacent polysilicon wiring (which is hereinafter referred to as a poly-space). That is, the size of the pattern in the semiconductor device is reduced and the integration density thereof is enhanced, and a charged beam exposure device or an optical stepper is used to draw and expose the pattern, but at this time, the dimensional precision of the pattern is lowered by the optical proximity effect.
FIGS. 1A and 1B are a plan view of a polysilicon wiring pattern and a characteristic diagram for illustrating the dependency of the wiring width on the space between the wirings which varies by the optical proximity effect. In FIG. 1B, the ordinate indicates the poly-width W (.mu.m) and the abscissa indicates the poly-space d (.mu.m). For example, when a plurality of polysilicon wirings with the poly-width W of 0.3 .mu.m are arranged in close proximity to one another, there occurs a phenomenon that the poly-width W is reduced to approx. 0.26 .mu.m when the poly-space d becomes approx. 1 .mu.m. Therefore, at the time of manufacturing the semiconductor device, it becomes absolutely necessary to make correction in order to enhance the dimensional precision of the pattern which is lowered by the optical proximity effect when the pattern for wirings or the like to be formed on the semiconductor device is drawn or exposed.
An OPC (Optical Proximity effect Correction) technique is considered as the technique for compensating for the optical proximity effect. The OPC technique is a technique for keeping the finish value of the poly-width after exposure at a constant value by estimating an amount of variation in the poly-width due to the optical proximity effect of the polysilicon wirings based on the distance between the polysilicon wiring and an adjacent polysilicon wiring pattern in close proximity thereto and previously correcting the mask value of a photoresist for forming the polysilicon wiring to cancel the variation amount. In the conventional layout, the polysilicon wiring pattern is not standardized, the poly-space is different depending on polysilicon wirings of the whole chip, and therefore, it is necessary to make corrections by the OPC technique for all of the polysilicon wirings on the chip.
The basic cell library used for laying out a conventional standard cell type semiconductor device or the like is shown in the plan views of basic cells of FIGS. 2A to 2C and FIG. 3, for example. FIG. 2A shows an A cell registered in the basic cell library and one. pair of diffusion regions 2 acting as source/drain regions are formed in a cell frame 1 in which a cell region is formed. The diffusion regions 2 include a p+ diffusion region 21 and an n+ diffusion region 22 and one polysilicon gate 3 is disposed to extend over the diffusion regions 21, 22. FIG. 2B shows a B cell registered in the basic cell library and two polysilicon gates 3 are disposed to extend over a p+ diffusion region 21 and n+ diffusion region 22. FIG. 2C shows a C cell registered in the basic cell library and three polysilicon gates 3 are disposed to extend over a p+ diffusion region 21 and n+ diffusion region 22. FIG. 3 shows an E cell registered in the basic cell library and three polysilicon gates 3 are disposed to selectively extend over p+ diffusion regions 211, 221 and n+ diffusion regions 212, 222.
FIGS. 4 and 5 are plan views of chips on which standard cells are laid out. On a chip 10, basic cells (A, B, C) registered in the basic cell library are placed. In the case of FIG. 4, the basic cells A, B, C are successively placed in an order of ABC in a preset portion of the chip. In the case of FIG. 5, the basic cells are successively placed in an order of CBA in a preset portion of the chip. The positional relation between a target polysilicon gate (D) 3 (which is hereinafter referred to as a poly-data D) in FIGS. 4 and 5 and a polysilicon gate (E, F) 3 (which is hereinafter referred to as a proximity poly-data E, F) in close proximity thereto on the chip 10 is explained. In the case of FIG. 4, the poly-data D is disposed in close proximity to the proximity poly-data E. The. proximity poly-data E is bent and a poly-space b1 between the poly-data D and a portion of the proximity poly-data E which is formed above the diffusion region 21 is larger than a poly-space b2 between the poly-data D and a portion of the proximity poly-data E which is formed above the diffusion region 22;. In the case of FIG. 5, the poly-data D is disposed in close proximity to the proximity poly-data F. Poly-spaces between the poly-data D and both end portions of the proximity poly-data F are b3 and b4. Therefore, if b2, b3 and b4 are set equal to each other, the poly-space b1 becomes larger than b4 (b1 &gt;b4).
Thus, the distance between the poly-data and the proximity poly-data is different depending on a difference in the placement of the basic cells on the chip.
Therefore, in the design process in the conventional manufacturing method of the semiconductor device, after the function design, logic design and layout design are performed, a mask value correction for formation of correct pattern is made by taking the. optical proximity effect into consideration.
FIG. 6 is a plan view of a basic cell for illustrating the mask value correction for a variation due to the optical proximity effect. As shown in FIG. 6, since the poly-width varies according to the, distance to the proximity poly-data, the poly-width of the poly-data G on the mask is increased (increased width c) while monitoring the relation between the poly-width of the poly-data G and the poly-space b. Thus, in the case of FIG. 6, the poly-width is changed according to the distance b to the adjacent poly-data.
The wiring pattern is formed in the chip forming process by use of a mask which has been subjected to the correction process for the optical proximity effect.
In most cases, the poly-datas which should be corrected by the OPC technique lie only in the cell region as shown in FIG. 6. Therefore, if the poly-width is corrected by the OPC technique not in the whole portion of the chip but in the respective cell regions, the number of poly-datas subjected to the OPC process is significantly reduced and the amount of processing is reduced. However, in the cells used now, as shown in FIG. 5, the distance from the poly-data used in the cell to the proximity poly-data is not definite inside the cell, and only when the standard cell is laid out on the chip, the distance from a preset poly-data (polysilicon gate) to an adjacent poly-data (proximity poly-data) is determined.
Further, since the distance from the poly-data to a proximity poly-data adjacent thereto varies even in the same cell depending on a cell disposed in an. adjacent position, the amount of variation in the poly-width due to the optical proximity effect is changed. Therefore, correction of the mask width of the poly-width by the OPC technique cannot be performed until the cell layout is completed, thereby causing a problem that the delay in TAT (Turn Around Time) and an increase in the amount of processing will occur.